1. Field of the Invention
The present invention relates to a process for manufacturing a wiring board having a via and, more specifically, to a method for forming a via penetrating a substrate made of an insulation material while filling metal, by plating in a through-hole formed in the substrate, so that a plated metallic layer of a predetermined thickness is formed on the surface of the substrate.
2. Description of the Related Art
A multi-layer wiring substrate shown in FIG. 6 is used in an electronic part such as a semiconductor device. In the multi-layer wiring substrate shown in FIG. 6, wiring patterns 102, 102, . . . formed on opposite surfaces of a core substrate 100 of an insulation material such as a ceramic, a resin or others, are electrically connected to wiring patterns 122, 122, . . . formed in insulation layers 120, 120, . . . made of an insulation material such as a resin or others by vias 104, 104, . . . formed to penetrate the core substrate 100 and vias 124, 124, . . . formed in the insulation layers 120, 120, . . . .
A method for manufacturing such a core substrate 100 is disclosed, for example, in Japanese Unexamined Patent Publication (Kokai) No. 2002-16357 (paragraphs [0034] to [0047], FIGS. 2 and 3).
The method for manufacturing the core substrate 100 described in the above-mentioned patent document will be explained below with reference to FIGS. 7(a) to 7(g).
First, a thick metallic layer 110 is formed on all surfaces of the core substrate 100, including an inner wall surface of a through-hole 106 bored in the core substrate 100 by a drill or others, by electrolytic plating in which a metallic layer 108 formed by electrolytic plating is used as a power supply layer (see FIGS. 7(a) and 7(b)).
Further, the through-hole 106, in which the metallic layers 108 and 110 are formed on the inner wall surface, is filled with resin 112, so that dome-like portions 112a are formed at opposite openings of the through-hole 106 (see FIG. 7(c)). Then, the metallic layer 110 is subjected to the etching while using the dome-like portion 112a as a mask and is thinned to be a thin metallic layer 110a (see FIG. 7(d)).
Then, the dome-like portion 112a is removed by the grinding or others so that an exposed surface of the resin 112 is flush with the surface of the thin metallic layer 110a (see FIG. 7(e)), and thereafter, a metallic layer 114 is formed on the thin metallic layer 110a and the exposed surface of the resin layer 112 by the electroless plating, whereby the via 104 penetrating the core substrate 100 is obtained (FIG. 7(f)).
Thereafter, the wiring patterns 102, 102, . . . of a desired shape are formed by patterning a multi-metallic layer consisting of the metallic layer 108, the thin metallic layer 110a and the metallic layer 114 (see FIG. 7(g)) to result in the core substrate 100 shown in FIG. 6.
According to the core substrate 100 shown in FIGS. 6 and 7(a) to 7(g), the wiring patterns 102 are formed on opposite ends of the vias 104, 104, . . . to facilitate the degree of freedom in the design of the wiring pattern 102.
However, as the via 104 of the core substrate 100 is formed of metal and resin, the electric properties thereof being largely different from each other, an improvement in electrical characteristics, such as impedance, is limited.
In this regard, it has been proposed to fill metal, by plating, in a through-hole, in advance, during the formation of a substrate made of an insulation material.
According to this method for forming the via, after forming a through-hole 202 in a substrate 200 made of an insulation material, as shown in FIG. 8(a), a seed layer 204 of metal is formed on a surface of the substrate 200 including an inner wall surface of the through-hole 202 by electroless plating as shown in FIG. 8(b).
Then, electrolytic plating is carried out while using the seed layer 204 as a power supply layer, to form a plated metallic layer 206 on the seed layer 204 as shown in FIG. 8(c).
When the electrolytic plating is continued, the through-hole 202 is filled with metal to complete the via as shown in FIG. 8(d), and the plated metallic layer 206 of a predetermined thickness is formed on the surface of the substrate 200.
Thereafter, the plated metallic layer 206 is patterned to form a desired wiring pattern on each of the opposite surfaces of the substrate 200. Thus, a wiring substrate having the via, both of which ends are connected to the wiring patterns, is obtained.
However, as shown in FIG. 8(d), a void 208 may possibly be generated in the via or dimples 210 and 210 may possibly be formed in the plated metallic layer 206 at positions corresponding to the center of the openings of the through-hole 202.
If the depth of such dimples 210 and 210 is smaller than a thickness of the plated metallic layers 206 formed on the respective surfaces of the substrate 200, it is possible to remove the dimples 210 and 210 by removing the plated metallic layer 206 by etching or other methods.
However, if the depth of the dimples 210 and 210 exceeds the thickness of the plated metallic layer 206 as shown in FIG. 9(a), the dimples 210 and 210 are not completely removable even if the plated metallic layer 206 is removed by etching or other methods.
Also, if the through-hole 202 is not completely closed to leave a thin hole (seam) 212 as shown in FIG. 9(b), the seam 212 is still left as it is even if the plated metallic layer 202 is removed by the etching or others.
In addition, a number of vias must be formed, in general, in the core substrate 100, and it is extremely difficult to optimize the plating condition for all the through-holes 202 formed in the substrate 200. Accordingly, there may be some vias having the dimple 210 or the seam 212 among the plurality of vias formed in the substrate 200.
There is a risk, in the substrate having vias in which dimples 210 or seams 212 exist, that the electric connection between the via and the wiring pattern becomes worse if the wiring pattern is formed directly on each of the opposite end surfaces of the respective via. Accordingly, in general, a wiring pad having a diameter larger than that of the through-hole 202 is provided on each of the opposite end surfaces of the via to ensure the electric connection between the both.
However, the provision of the wiring pad having the larger diameter on each of the opposite end surfaces of the respective via is problematic in that the degree of freedom is reduced in the design of wiring pattern formed in the substrate, and a high-density arrangement of the wiring pattern becomes difficult.